Silicon wafers represent the primary bottleneck in the 2026 random access memory (RAM) shortage as high-end artificial intelligence (AI) endeavors have driven up prices, even for consumer electronics.
In October last year, a silent yet seismic shift occurred in the tech world. OpenAI, the artificial intelligence (AI) giant, announced a strategic partnership with Samsung and SK Hynix to fuel its expanding data centers as part of the Stargate initiative (1). Through this, OpenAI anticipated to secure and purchase 900,000 dynamic random-access memory (DRAM) wafers monthly in order to power advanced AI models. While this partnership itself was a standard business deal, the ripple effects were immediate. The sudden increase in demand drove up the price of memory modules drastically, squeezing other consumers and manufacturers who were already operating on razor-thin margins.
Behind every AI model, smartphone, and electric vehicle is a silicon wafer, a thin disc of crystalline silicon that acts as the canvas for modern electronics. When demand spikes, as it has with the AI boom, the industry cannot simply flip a switch to produce more. The reason lies in the complexity of semiconductor manufacturing, which involves high-stakes chemistry and physics and pushes the boundaries of precision. To understand why the supply chain is so rigid, one must look beneath the surface of the microchip.
From sand to silicon: the Czochralski process
Silicon is the second-most abundant element in the Earth’s crust, found in sand. However, the silicon for chips must be purified to a target purity of at least “nine nines” — 99.9999999% (2). Any impurity at this level can act as a defect.
Creating the substrate for a chip involves growing a single crystal ingot. Using the Czochralski method, a seed crystal is dipped into molten silicon and slowly pulled upward while rotating. The molten silicon solidifies onto the seed, forming a cylindrical ingot. This is a thermal process governed by strict heat transfer rates. Pull it too fast, and the crystal structure fractures or develops internal stresses. Pull it too slow, and production costs increase. Once the ingot is grown, it must cool down slowly over days to prevent warping. Only then is it sliced into wafers, lapped, and polished until the surface is smoother than a mirror. This entire cycle, from sand to finished wafer, takes weeks.
Once the wafer arrives at the fabrication plant, or “fab,” billions of microscopic transistors have to be built on a surface the size of a fingernail. This is achieved through a process called photolithography. The wafer is coated with a light-sensitive chemical called photoresist. When exposed to ultraviolet light through a mask, the photoresist changes its solubility. This allows engineers to “draw” the circuit patterns onto the chemical layer.
Precision in photolithography
Precision is one of the most important factors in producing silicon wafers. Modern chips include features smaller than the wavelength of visible light. To achieve this, manufacturers use extreme ultraviolet lithography. The photochemical reactions must be controlled with nanometer accuracy. If the exposure time is off by a fraction of a second, or if the temperature of the photoresist varies slightly, the pattern blurs. A blurred pattern means a short circuit, and a short circuit means the entire wafer is scrap. The chemical reactions involved in developing the resist must be uniform across a 300-mm disc.
Etching the wafer
After the pattern is defined, the wafer must be etched. Etching is the process of removing material to create the trenches and connections that form the circuit. For modern chips, plasma etching is preferred, where gases are ionized into a state of matter that contains charged particles. These ions bombard the wafer surface, physically and chemically stripping away material. Controlling this process requires a delicate balance. If the etch is too aggressive, it eats into the layers below, ruining the device. If it is too gentle, the circuit remains blocked.
Doping and thermal annealing
Following patterning and etching, its conductivity must be modified through doping, specifically via ion implantation. In this process, boron or phosphorus ions are fired at precise speeds into the silicon lattice.
This bombardment damages the crystal structure, which is repaired through rapid thermal annealing. This brief, high-heat treatment realigns the lattice and integrates the dopants. Precise thermal management is critical; any temperature variation across the wafer can cause uneven dopant diffusion, leading to chip failure.
Inside the cleanroom
All of these steps take place in a cleanroom. Inside, air is filtered to particle limits between 352 particles/m3 and 35,200 particles/m3 at 0.5 μm for cleanrooms Class 4–6 (3) to prevent even a single speck of dust from ruining a chip. To maintain this, ventilation systems use high-efficiency particulate air (HEPA) or ultra-low particulate air (ULPA) filters and laminar flow to sweep away contaminants, while temperature and humidity are strictly regulated to ensure chemical stability and precise layer alignment. Even workers must wear full bunny suits and follow rigid movement protocols, as any stray skin cell or hair could bridge circuits and render a costly wafer worthless.
Why production can't be rushed
When we combine the time and attention to detail required for all these factors, we see why production cannot be accelerated, and building additional fabs isn’t in itself an option. A single wafer might stay in the fab for three to four months. It is not a continuous-flow line like making soda; it is a batch process where each wafer moves through various stations, waiting its turn. While every smartphone, laptop, and smart appliance contains these silicon wafers, high-end computing systems (both consumer and commercial electronics) are heavily dependent on ultra-pure wafers, sometimes even necessitating target purity levels of “eleven nines”— 99.999999999%.
The steady rise in DRAM prices
Following OpenAI’s announcement, DRAM prices — which had remained largely stable since 2023 — skyrocketed. Depending on memory size, prices have surged three to five times their original value. For AI workstations, the impact is even more severe: 256 GB of DDR5 DRAM has jumped from an average of $1,700 in October 2025 to over $8,000 in April 2026 (4). Prices may eventually start to drop, but it will take time to get back to where it all started.
What this means for the chemical engineering community
For the chemical engineering community, this production bottleneck presents both a challenge and an opportunity. The industry is constantly seeking new materials, such as silicon carbide or gallium nitride, which offer better performance but bring their own processing difficulties (5). Simultaneously, there is a push for “green” manufacturing to mitigate the massive water and energy footprints of modern fabs. Ultimately, the future of computing depends not just on more efficient code, but on breakthroughs in chemistry and engineering.
- “Samsung and SK Join OpenAI’s Stargate Initiative to Advance Global AI Infrastructure,” OpenAI, https://openai.com/index/samsung-and-sk-join-stargate (Oct. 1, 2025).
- “About Silicon,” Addison Semiconductor Materials, https://www.addisonengineering.com/about-silicon.html (accessed Apr. 1, 2026).
- “What are Semiconductor Cleanrooms? Here’s What You Need To Know,” Angstrom Technology, https://angstromtechnology.com/what-are-semiconductor-cleanrooms (Dec. 15, 2025).
- “256GB DDR5 Price History Chart (April 2026),” Pangoly, https://pangoly.com/en/price-trends/ram/256gb-ddr5 (accessed Apr. 7, 2026).
- Lapedus, M., “Inspection, Metrology Challenges Grow For SiC,” Semiconductor Engineering, https://semiengineering.com/inspection-metrology-challenges-grow-for-sic (June 11, 2019).
This article originally appeared in the Emerging Voices column in the May 2026 issue of CEP. Members have access online to complete issues, including a vast, searchable archive of back-issues found at www.aiche.org/cep. Learn more about AIChE membership.
